1. Field
Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device including a plurality of contacts.
2. Description of the Related Art
As the semiconductor device fabrication technology has been remarkably enhanced, the integration degree of a semiconductor device is significantly increased to reduce the size of the semiconductor device. As memory devices such as a Dynamic Random Access Memory (DRAM) device achieve high integration degree, cell structures are changing from 8F2 to 6F2, where F denotes the minimum line width applied to a design rule.
FIG. 1 is a plan view illustrating a conventional semiconductor device having a 6F2 cell structure.
Referring to FIG. 1, the conventional semiconductor device includes a plurality of active regions 11, gate lines 12, and bit lines 13. The active regions 11 have a shape of island having a long axis and a short axis and the long axis is disposed to be slanted at an acute angle to a first direction. The gate lines 12 are stretched in a second direction crossing the active regions 11. The bit lines 13 are stretched in a first direction crossing the active regions 11.
The gate lines 12 are disposed to cross in such a manner that two gate lines 12 cross one active region 11. Each active region 11 is divided into three parts by the two gate lines 12: two parts disposed in the exterior of the two gate lines 12, which are referred to as edge parts hereinafter, and a central part between the two gate lines 12. Each of the two edge parts may be a region to be coupled with a storage node (not shown) and the central part may be a region to be coupled with a bit line 13.
As shown, the active regions 11 are arrayed in the first direction in such a manner that the central parts are disposed on a line stretched B-B′ in the first direction. Also, the active regions 11 are arrayed in the second direction in such a manner that one edge part, the other edge part, and the central part are alternately disposed on a line A-A′ stretched in the second direction.
The bit lines 13 overlap with the central parts that are arrayed in the first direction, and are coupled with the central parts of the active regions 11 directly or with a conductive material interposed between them. Also, storage nodes (not shown) are coupled with the edge parts of the active regions 11 directly or with a conductive material interposed between them.
However, diverse concerns may appear in the process of fabricating such a type of the semiconductor device. One of them may be occurring in the process of forming bit line contacts and storage node contacts that are respectively coupled with the central parts and the edge parts of the active regions 11. When contact holes are formed to form storage node contacts or bit line contacts according to the conventional technology, holes may be formed to have a narrow width due to technical limitation in exposure and development processes. Therefore, it may be difficult to perform a subsequent process, for example, a process of forming storage nodes over the storage node contacts. Also, misalignment may occur in a formation of the contacts for edge parts or formation of the contacts for central parts. In particular, since the edge parts and the central parts may be disposed close to each other in the conventional semiconductor device, when misalignment occurs, for example, a storage node contact may be un-desirably coupled to the central part of the active region 11. As a result, the production yield of the semiconductor device may be seriously deteriorated.
To address the above concerns, a line type opening forming technique has been introduced. The line type opening forming technique includes forming a line type opening having a relatively wide width then that of contact holes, filling the line-type opening with a conductive material, and isolating the conductive material in a subsequent process. However, since the edge parts and the central parts of the active regions 11 are arranged on the A-A′ line of FIG. 1 and the edge parts may be disposed closely to the central parts of the active regions 11 in the conventional semiconductor device, not only the portion to be exposed by the line-type opening, for example, the edge part, but also the other parts, for example, undesirable parts, i.e., the central part, may be exposed.